Architecting Neuromorphic SoCs With ReRAM and Open-Source Tools

Taking a neuromorphic compute idea from a theoretical concept to a fabricated silicon chip traditionally requires millions of dollars in proprietary EDA tools and foundry agreements. In this session, Samarth Jain from BM LABS details how to bypass those barriers using open-source toolchains. By pairing non-volatile Resistive RAM (ReRAM) IP with the open-source ASIC pipeline, developers can seamlessly architect event-driven Systems-on-Chip (SoCs) ready for tape-out on the SkyWater SKY130 process.

Key Takeaways

• ReRAM mirrors synaptic plasticity: By migrating metal ions to form or break filaments, ReRAM controls resistive states similarly to how biological synapses manage calcium ions. This physical, non-volatile state retention is ideal for extremely low-latency, always-on edge devices.
• Caravel simplifies the silicon wrapper: The open-source Caravel harness supplies a complete “wrapper” including a PicoRV32 RISC-V processor and mixed-signal I/O pads. This allows designers to simply hook their custom accelerator’s Wishbone bus into the master without routing basic microcontroller infrastructure.
• OpenLane automates the physical layout: Once a behavioral model is written and validated (e.g., via CocoTB), OpenLane automates synthesis, placement, routing, and design rule checking (DRC/LVS), outputting a factory-ready GDSII file entirely using free tools.
• Embedded NVM enables ultra-low latency: The X1 IP places a 32x32 1T1R crossbar array directly on-chip. Because the memory is embedded and non-volatile, the system achieves deterministic latency critical for robotics and industrial sensors, avoiding the bottleneck of fetching from external DRAM.
• Compute-in-Memory (CIM) minimizes data movement: By exploiting Ohm’s law for multiplication and Kirchhoff’s current law for accumulation, future X2 IPs allow dot-product operations to occur physically inside the memory crossbar, drastically cutting the energy tax of data transport.

What Was Built / Demonstrated

The session featured a comprehensive walkthrough of testing and routing an open-source SoC. Using CocoTB (a Python-based testbench tool), the team simulated a behavioral Verilog model of the X1 ReRAM IP, writing row addresses and data via the Wishbone interface and examining the timing diagrams.

Following the timing validation, the code was processed through OpenLane to automatically generate the physical layout. The resulting GDSII file was then inspected using KLayout, demonstrating exactly how the custom crossbar array physically interfaces with the Caravel harness’s routing tracks and risk-V processor pins.

What This Means for Neuromorphic Computing

Historically, researchers working on neuromorphic algorithms have been confined to FPGA emulation or software simulation. This open-source hardware stack fundamentally democratizes neuromorphic ASIC design.

By utilizing mature open-source tools like OpenLane and Caravel, hardware engineering students and practitioners can now design, simulate, and physically manufacture custom neuromorphic architectures. Access to affordable, CMOS-compatible embedded non-volatile memory bridges the gap between academic theory and deployable, brain-inspired edge hardware.

Resources

• Video: Watch the session on YouTube