The TSP1 is a time-series neural network accelerator chip designed for ultra-low power edge AI applications, delivering full vocabulary speech recognition at 100x lower power than traditional edge GPU solutions while supporting state-space network processing for real-time time-series inference.
Developed By:
Overview
The Applied Brain Research TSP1 is a groundbreaking time-series neural network accelerator designed to bring advanced AI capabilities to battery-powered edge devices. The chip enables natural voice interfaces, biosignal classification, and other sensor signal processing applications with unprecedented power efficiency. Based on ABR’s patented state-space model processing technology, including the Legendre Memory Unit (LMU), the TSP1 represents a paradigm shift in how time-series data is processed at the edge.
The TSP1 was publicly demonstrated in September 2025 as the world’s first self-contained single-chip solution for full vocabulary automatic speech recognition, showcasing both English and Mandarin implementations. The chip delivers 100x lower power consumption compared to edge GPU solutions while supporting AI models 10-100x larger than other low-power edge AI hardware.
Architecture
The TSP1 features a specialized architecture optimized for time-series processing:
Processing Core:
- High-efficiency neural processing element fabric based on ABR’s proprietary state-space network architecture
- 32-bit RISC microcontroller unit (MCU) for control and preprocessing
- Supports up to 9 million 8-bit or 18 million 4-bit state-space neural network parameters
- Integrated weight memory and SRAM for on-chip model storag
- Secure on-chip non-volatile storage for networks and firmware
Power and Performance:
- Voltage range: VDD 1.65-3.6V with integrated 0.8V core DC-DC supply
- Keyword spotting trigger function: <2mW
- Full vocabulary speech recognition: <50mW
- Low latency inference for full vocabulary ASR: <120ms
- Integrated low-power PMU and clock management
Interfaces:
- Up to 4 stereo audio inputs
- One TDM streaming output
- SPI and I2C master interfaces for sensor integration
- I2C and SPI target interface for host CPU communication
- Multiple programmable GPIO pins
- UART support
Package Options:
- 42-pin WLCSP (0.5mm pitch)
- 44-pin QFN package
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